|The Intel® XScale™ microarchitecture is based on a new core which is compliant with ARM* version 5TE. The microarchitecture surrounds the core with instruction and data memory management units; instruction, data, and mini-data caches; write, fill, pend, and branch target buffers; power management, performance monitoring, debug, and JTAG units; coprocessor interface; 32K caches; MMUs; BTB; MAC coprocessor; and core memory bus. The Intel XScale microarchitecture will be combined with peripherals to provide applications specific standard products (ASSP) targeted at selected market segments. As an example, the RISC core can be integrated with peripherals such as an LCD controller, multi-media controllers and an external memory interface to empower OEMs to develop smaller, more cost-effective handheld devices with long battery life, with the performance to run rich multimedia applications. As another example, the microarchitecture could be surrounded by high-bandwidth PCI interfaces, memory controllers and networking microengines to provide a highly integrated, low power, I/O or network processor.
- 7-8 stage Intel® Superpipelined RISC Technology achieves high speed and ultra low power
- Intel® Dynamic Voltage Management. Dynamic voltage & frequency on-the-fly scaling allows applications to utilize the right blend of performance and power
- Intel® Media Processing Technology. Multiply-accumulate coprocessor performs two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient media processing
- Power management unit gives power savings via idle, sleep and quick wake-up modes.
- 128-entry branch target buffer keeps pipeline filled with statistically correct branch choices
- 32 KB instruction cache keeps local copy of important instructions to enable high performance and low power
- 32 KB data cache keeps local copy of important data to enable high performance and low power
- 2 KB mini-data cache avoids “thrashing” of the d-cache for frequently changing data streams
- 32-entry instruction memory management unit enables logical-to-physical address translation, access permissions, i-cache attributes
- 32-entry data memory management unit enables logical-to-physical address translation, access permissions, d-cache attributes
- 4-entry fill and pend buffers promotes core efficiency by allowing “hit-under-miss” operation with data caches
- Performance monitoring unit furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc.
- Debug unit uses hardware breakpoints and 256-entry trace history buffer (for flow change messages) to debug programs
- 32-bit coprocessor interface provides high performance interface between core and coprocessors
- 64-bit core memory bus with simultaneous 32-bit input path and 32-bit output path gives up to 4.8 GBytes/sec. @ 600 MHz bandwidth for internal accesses
- 8-entry write buffer allows the core to continue execution while data is written to memory