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ARM1136JF-S Processors    
ARM1136JF-S





ARM1136JF-S
The award-winning ARM1136J-S™ and ARM1136JF-S™ deliver up to 660 Dhrystone 2.1 MIPS in 0.13µ process. Both cores feature the ARM v6 instruction set with media extensions, ARM Jazelle™ technology for efficient embedded Java execution, ARM Thumb ® code compression, and optional floating point coprocessor.
Media processing extensions offer up to 1.9x acceleration of media-processing tasks such as MPEG4 encode. Instruction and data cache sizes are and optional Tightly Coupled Memories can be added to accelerate interrupt handling and data-processing. These cores feature AMBA 2.0 AHB interfaces compatible with a wide range of system IP and peripherals.
The ARM1136JF-S also features an integrated floating point coprocessor, which makes it particularly suitable for embedded 3D-graphics applications.
The ARM11 core has been developed and integrated in parallel with the ARM11 PrimeXsys Platform to ensure a fully compatible, high performance, extendable system solution. As a result, the ARM11 PrimeXsys Platform provides the optimum route to the efficient and rapid implementation of an ARM11 core-based design.
  • Networking – Control processor in network infrastructure, switch, and router products
  • Consumer – Digital TV, Set-top Box, Games Console
  • Automotive infotainment – in-Car entertainment, DVD player, navigation equipment


Features:
  • Powerful ARMv6 instruction set architecture
    • ARM Thumb instruction set reduces memory bandwidth and size requirements by up to 35%
    • ARM Jazelle technology for efficient embedded Java execution
    • ARM DSPextensions
    • SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing
  • Energy-saving power-down modes
    • Reduce static leakage currents when processor is not in use
  • High performance integer processor
    • 8-stage integer pipeline delivers high clock frequency
    • Separate load-store and arithmetic pipelines o Branch Prediction and Return Stack
    • Up to 660 Dhrystone 2.1 MIPS in 0.13µ process
  • High performance memory system
    • Supports 4-64k cache sizes o Optional tightly coupled memories with DMA for multi-media applications
    • Multi-ported AMBA 2.0 AHB bus interface speeds instruction and data access
    • ARMv6 memory system architecture accelerates OS context-switch
  • Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance
    • Optional Vector Floating Point coprocessor (ARM1136JF-S)
    • Powerful acceleration for embedded 3D-graphics
    • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.