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ARM Cortex-M3 Processors    
ARM Cortex-M3

ARM Cortex-M3

The ARM Cortex-M3™ processor has been developed to provide a high-performance low-cost platform that meets the needs of minimal memory implementation, reduced pin count and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

The ARM Cortex-M3 32-bit RISC processor executes purely Thumb®-2 instructions, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

In addition to minimizing its memory requirement, the ARM Cortex-M3 processor is also the smallest 32-bit core designed by ARM at just 33k gates for the processing core and 60k gates total, including many close system peripherals. This design reduces silicon area requirements even further, enabling the smallest of packages or the manufacturing of devices on low-cost processes, such as 0.35uM and 0.25uM.

The ARM Cortex-M3 processor also reduces the number of pins required for debug from five to one, by implementing a new debug interface technology - Single Wire Debug - that can replace the current multi-pin JTAG port.

Outstanding Performance

In addition to unparalleled performance, power consumption and memory utilization, the ARM Cortex-M3 processor also achieves exceptional interrupt handling. By implementing the register manipulations required for handling an interrupt in hardware this core achieves minimal clock overhead on entering interrupts, and switches between pending or higher priority interrupts in only six cycles. The design, which comes with 32 interrupt channels as standard can be configured to between 1 and over 240 channels.

The ARM Cortex-M3 processor also includes an optional memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

Enabling Technology

The ARM Cortex-M3 processor has been designed ‘from the ground up’ to provide optimal performance and power consumption within a minimal memory system. To achieve this the core executes only the Thumb-2 instruction set, which delivers an unparralled combination of ARM instruction set performance with industry leading code density. The design, which is based on a 3-stage pipeline Harvard architecture, also maximizes memory utilization through the support of unaligned date storage, and single cycle atomic bit manipulation.

The exceptional performance of the ARM Cortex-M3 processor is achieved through a highly revised architecture that also implements many new technologies in this type of core, such as hardware divide and single cycle multiply.