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ARM966E-S Processors    


Embedded Core with Flexible Memory System & DSP Instruction Set Extensions

The ARM966E-S macrocell is a fully synthesizable 32-bit RISC core aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations, and 16-bit fixed point DSP instructions to accelerate signal processing algorithms and applications. The ARM966E-S core has separate directly connected instruction and data tightly coupled memory (TCM), which have flexible sizes and run at the processor clock speed. The ARM966E-S supports ARM's real-time trace technology with the optional ETM9 Embedded Trace Macrocell. The ARM966E-S features a simple memory map providing an area and power efficient solution for applications which do not require complex memory management support. The core includes an AMBA bus-compliant AHB interface, and a coprocessor interface for connection to application acceleration hardware such as the VFP9-S floating point coprocessor.

  • Mass storage devices
    • Hard disc drives, DVD drives
  • Networking systems
  • Automotive control
    • Powertrain with VFP9-S coprocessor
  • Wireless devices
  • Digital still cameras
  • 32/16-bit RISC architecture (ARMv5TE)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased code density
  • Tightly Coupled Memories (TCMs)
  • EmbeddedICE-RT logic for real-time debug
  • Floating point capability with VFP9-S coprocessor
  • ETM interface for Real-time trace capability with ETM9
  • ARM-Synopsys Reference Methodology compliant deliverables
  • Optional MOVE coprocessor delivers video encoding performance
  • Single chip MCU and DSP solution
  • Deterministic performance from TCM memories
  • Simple single-processor software structure
    • No need for software partitioning across MCUs
    • Eliminates multi-MCU debugging
  • Single development toolkit:
    • Reduced development costs and shorter development cycle time
  • Optimized for hard real-time applications
  • Multiple sourcing from industry-leading silicon vendors
  • Code-compatible upward migration path to ARM10E family
  • Excellent debug support for SoC designers
  • Instruction set can be extended by the use of coprocessors
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.