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ARM7TDMI-S Processors    

Synthesizable ARM7TDMI™ 32-bit RISC performance at 8-/16-bit system cost
The ARM7TDMI-S core is a synthesizable, 32-bit embedded RISC processor. It builds on the features and benefits of the established ARM7TDMI core and is delivered ready for synthesis. The ARM7TDMI-S core provides system designers with the flexibility necessary to build embedded devices requiring small size, low power and high performance. The ARM7 family also includes the and cores and the macrocell, each of which has been developed to address different market requirements.
  • Personal audio (MP3, WMA, AAC players)
  • Entry level wireless handset
  • Pager
  • Ink-jet/bubble-jet printer
  • Digital still camera  
  • 32/16-bit RISC architecture (ARM v4T)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased code density
  • Unified bus interface, 32-bit data bus carries both instructions and data
  • Three-stage pipeline
  • 32-bit ALU
  • Very small die size and low power consumption
  • Fully static operation
  • Coprocessor interface
  • Extensive debug facilities:
    • EmbeddedICE-RT real-time debug unit
    • JTAG interface unit
    • Interface for direct connection to Embedded Trace Macrocell (ETM)
  • Synthesizable design can be ported to many process technologies and optimized for speed or size
  • Unified memory bus simplifies SoC integration process
  • ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
  • Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9,ARM9E and ARM10 families
  • Small die size reduces overall SoC area, cost and power consumption
  • Static design and lower power consumption are essential for battery-powered devices
  • Scannable design means high levels of testability can be achieved
  • Instruction set can be extended for specific requirements using coprocessors
  • EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.