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ARM968E-S Processors    
ARM968E-S





ARM968E-S
Low Power, Small Footprint Embedded Core for Deeply Embedded Systems

The ARM968E-S macrocell is a fully synthesizable 32-bit RISC processor aimed specifically at embedded real-time applications, and is the smallest, lowest power  ARM9E  family processor to date. The processor implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations, and 16-bit fixed point  DSP  instructions to accelerate signal processing algorithms and applications. The ARM968E-S processor has separate directly connected instruction and data tightly coupled memory (TCM), which have flexible sizes. The ARM968E-S processor also features a dedicated AHB-lite slave Direct Memory Access (DMA) port and dual banked data TCM to enable the processor and a DMA controller to share access to TCM. The ARM968E-S processor supports ARM's real-time trace technology with the optional  ETM9  Embedded Trace Macrocell. The core includes a low latency  >AMBA  AHB-lite bus-compliant master interface for efficient connection to peripheral devices and for rapid response to system interrupts.

Applications:

  • Networking systems
    • Wireless LAN
    • 802.11
    • Firewire
    • SCSI
  • Wireless devices
  • Mass storage devices
    • Hard disc drives
  • Automotive
  • Consumer
    • Audio players

Features:

  • 32/16-bit RISC architecture (ARMv5TE)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit  Thumb  instruction set for increased code density
  • Low latency AHB-lite bus master interface
  • Low latency AHB-lite bus slave DMA interface
  • Configurable Tightly Coupled Memories (TCMs)
  • Dual banked data TCM
  • EmbeddedICE-RT logic for real-time debug
  • ETM interface for Real-time trace capability with  ETM9

Benefits:

  • Smallest, lowest power ARM9E Family CPU (gate count = 80% of ARM966E-S)
  • Low latency bus interfaces, reducing power consumption and improving responsiveness
  • Dual banked TCM memories providing full bandwidth access by the core and DMA to optimize memory bandwidth
  • Highly efficient packet processing and data throughput
  • Simple single-processor software structure
    • No need for software partitioning across MCUs
    • Eliminates multi-MCU debugging
  • Single development toolkit:
    • Reduced development costs and shorter development cycle time
  • Optimized for hard real-time applications
  • Multiple sourcing from industry-leading silicon vendors
  • Code-compatible upward migration path to other cached ARM9E family cores and the ARM10E family
  • Excellent debug support for SoC designers
  • ARM-EDA  Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.