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Embedded Core with Flexible Cached Memory System & DSP Instruction Set Extensions

The ARM946E-S™ is a synthesizable macrocell well suited to a wide range of embedded applications. It combines an ARM9E-S™CPU with flexible instruction and data caches, instruction and data tightly coupled memory (TCM) interfaces, a protection unit, and an AMBA bus compliant AHB interface. The size of the instruction and data cache, and instruction and data TCM memories are configurable to allow tailoring of the hardware to the embedded application. The ARM946E-S supports ARM's real-time trace technology with the addition of the optional ETM9 macrocell. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations, and 16-bit fixed point DSP instructions to accelerate signal processing algorithms and applications. The ARM946E-S provides a complete high-performance processor solution, reducing system complexity, die size, power consumption and time-to-market.

ARM Foundry Program
A hardened implementation of the ARM946E macrocell is available via the ARM Foundry Program


  • Embedded applications running an RTOS
  • 2.5G and 3G baseband processor
  • Speech codecs
  • Imaging products
    –Printers, digital cameras
  • Networking systems
  • Automotive control
    –Powertrain with optional VFP9-S floating point coprocessor


  • 32/16-bit RISC architecture (ARMv5TE)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased code density
  • Memory Protection Unit (MPU) supporting all major RTOS: Vxworks, pSOS
  • Flexible instruction and data cache sizes
  • Instruction and data TCM interfaces
  • Industry standard AMBA AHB interface
  • Floating point support with the optional VFP9-S coprocessor
  • EmbeddedICE-RT logic for real-time debug
  • ETM interface for Real-time trace capability with ETM9
  • ARM-Synopsys Reference Methodology compliant deliverables
  • Optional MOVE Coprocessor delivers video encoding performance


  • Single chip MCU & DSP capable core
  • No duplication of on-chip memory, bussing, debug or trace resources
  • Process portable synthesisable design
  • Single unified software development and debug environment:
  • Multiple sourcing from industry-leading silicon vendors
  • Code-compatible upward migration path to the ARM10E family
  • Excellent debug support for SoC designers
  • Fast interrupt response and context switch.
  • Performance split between DSP and controller code can vary dynamically, as system requirements change.
  • Instruction set can be extended by the use of coprocessors
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.